Interrupt Control Registers - Renesas H8 Series Hardware Manual

3.3.2

Interrupt Control Registers

Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name
Interrupt edge select register 1
Interrupt edge select register 2
Interrupt enable register 1
Interrupt enable register 2
Interrupt enable register 3
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
Note: * Write is enabled only for writing of 0 to clear a flag.
Interrupt Edge Select Register 1 (IEGR1)
Bit

Initial value

Read/Write
IEGR1 is an 8-bit read/write register used to designate whether pins IRQ
edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70.
Bit 7    Reserved Bit: Bit 7 is reserved: it is always read as 0 and cannot be modified.
Bits 6 to 4    Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be
modified.
Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ
Bit 3    IRQ
3
Bit 3: IEG3 Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Abbreviation
IEGR1
IEGR2
IENR1
IENR2
IENR3
IRR1
IRR2
IRR3
7 6 5
 
0 1 1
 
pin input is detected
3
pin input is detected
3
Section 3 Exception Handling
R/W Initial Value
R/W H'70
R/W H'00
R/W H'10
R/W H'00
R/W H'00
R/W *
H'10
R/W *
H'00
R/W *
H'00
4 3 2

IEG3 IEG2
1 0 0

R/W R/W
3
Rev. 6.00 Sep 12, 2006 page 63 of 526
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF5
H'FFF6
H'FFF7
H'FFF8
H'FFF9
1 0
IEG1 IEG0
0 0
R/W R/W
to IRQ
are set to rising
0
.
3
(initial value)
REJ09B0326-0600