Control Registers; Interrupt Control Registers 0 To 63 (Pic0 To Pic63) - Renesas NU85E Preliminary User's Manual

8.3.4 Control registers

(1) Interrupt control registers 0 to 63 (PIC0 to PIC63)

The interrupt control registers, which are assigned to each interrupt request (maskable interrupt), set control
conditions for each interrupt.
These registers can be read or written in 8-bit or 1-bit units.
Figure 8-8. Interrupt Control Registers 0 to 63 (PIC0 to PIC63)
7 6
PICn PIFn PMKn
Bit position Bit name
7 PIFn
6 PMKn
2 to 0 PPRn2 to
PPRn0
Remark n = 0 to 63
CHAPTER 8 INTC
5 4
0 0
This is the interrupt request flag.
0: No interrupt request issued
1: Interrupt request issued
When the interrupt request is acknowledged, this is automatically cleared (0).
This is the interrupt mask flag.
0: Interrupt service enabled
1: Interrupt service disabled (pending)
Specifies eight priority levels for each interrupt.
PPRn2 PPRn1 PPRn0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Preliminary User's Manual A14874EJ3V0UM
3 2 1
0 PPRn2 PPRn1
Function
Interrupt priority
Specifies level 0 (highest)
Specifies level 1
Specifies level 2
Specifies level 3
Specifies level 4
Specifies level 5
Specifies level 6
Specifies level 7 (lowest)
0
Address After reset
PPRn0
FFFFF110H to
FFFFF18EH
47H
221