Figure 12.47 Contention Between Tcnt Write And Clear Operations; Figure 12.48 Contention Between Tcnt Write And Increment Operations - Renesas H8S/2437 Hardware Manual

Contention between TCNT Write and Clear Operations:
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
priority and the TCNT write is not performed. Figure 12.47 shows the timing in this case.
φ
Address
Write signal
Counter clear
signal
TCNT

Figure 12.47 Contention between TCNT Write and Clear Operations

Contention between TCNT Write and Increment Operations:
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes priority and
TCNT is not incremented. Figure 12.48 shows the timing in this case.
φ
Address
Write signal
TCNT input
clock
TCNT

Figure 12.48 Contention between TCNT Write and Increment Operations

Rev. 1.00, 09/03, page 358 of 704
TCNT write cycle
T T
1 2
TCNT address
N H'0000
TCNT write cycle
T T
1 2
TCNT address
N M
TCNT write data