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12.3.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by WDT overflows.
7
Bit
WOVF
Bit Name
0
Initial Value
R/(W)*
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit
Bit Name
7
WOVF
6
RSTE
5
4 to 0
Note:
Only 0 can be written to this bit, to clear the flag.
*
6
5
RSTE
0
0
R/W
R/W
Initial
Value
R/W
Description
0
R/(W)* Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written.
[Setting condition]
When TCNT overflows (changed from H'FF to H'00) in
watchdog timer mode
[Clearing condition]
Reading RSTCSR when WOVF = 1, and then writing 0 to
WOVF
0
R/W
Reset Enable
Specifies whether or not this LSI is internally reset if
TCNT overflows during watchdog timer operation.
0: LSI is not reset even if TCNT overflows (Though this
1: LSI is reset if TCNT overflows
0
R/W
Reserved
Although this bit is readable/writable, reading from or
writing to this bit does not affect operation.
All 1
R
Reserved
These are read-only bits and cannot be modified.
4
3
1
1
R
R
LSI is not reset, TCNT and TCSR in WDT are reset)
Rev.2.00 Jun. 28, 2007 Page 441 of 666
Section 12 Watchdog Timer (WDT)
2
1
1
1
R
R
REJ09B0311-0200
0
1
R
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