Dma Mode Control Register (Dmdr) - Renesas H8SX/1520 Series Hardware Manual

Section 7 DMA Controller (DMAC)
Table 7.1 Data Access Size, Valid Bits, and Settable Size
Mode
Repeat transfer
and block transfer
7.2.6

DMA Mode Control Register (DMDR)

DMDR controls the DMAC operation.
• DMDR_0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.
Rev. 3.00 Mar. 14, 2006 Page 142 of 804
REJ09B0104-0300
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Data Access Size BKSZH Valid Bits BKSZ Valid Bits
Byte
Word
Longword
31 30
DTE DACKE TENDE
0 0
R/W R/W R/W
23 22
ACT —
0 0
R R
15 14
DTSZ1 DTSZ0 MDS1
0 0
R/W R/W R/W
7 6
DTF1 DTF0 DTA
0 0
R/W R/W R/W
31 to 16 15 to 0
29 28 27
— DREQS
0 0 0
R/W R/W
21 20 19
— — ERRF
0 0 0
R R R/(W)*
13 12 11
MDS0 TSEIE
0 0 0
R/W R/W
5 4 3
— —
0 0 0
R R
Settable Size
(Byte)
1 to 65,536
2 to 131,072
4 to 262,144
26 25
NRD —
0 0
R/W R
18 17
— ESIF DTIF
0 0
R R/(W)* R/(W)*
10 9
— ESIE DTIE
0 0
R R/W R/W
2 1
DMAP2 DMAP1 DMAP0
0 0
R/W R/W R/W
24
—
0
R
16
0
8
0
0
0