Dma Mode Control Register (Dmdr); Table 7.1 Data Access Size, Valid Bits, And Settable Size - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
Table 7.1 Data Access Size, Valid Bits, and Settable Size
Mode Data Access Size BKSZH Valid Bits BKSZ Valid Bits
Repeat transfer Byte
and block transfer
Word
Longword
7.2.6

DMA Mode Control Register (DMDR)

DMDR controls the DMAC operation.
• DMDR_0
Bit 31
Bit Name DTE
Initial Value 0
R/W R/W
Bit 23
Bit Name ACT
Initial Value 0
R/W R
Bit 15
Bit Name DTSZ1
Initial Value 0
R/W R/W
Bit 7
Bit Name DTF1
Initial Value 0
R/W R/W
Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.
Rev. 3.00 Mar. 14, 2006 Page 142 of 804
REJ09B0104-0300
31 to 16
30 29
DACKE TENDE
0 0
R/W R/W
22 21
— —
0 0
R R
14 13
DTSZ0 MDS1 MDS0
0 0
R/W R/W
6 5
DTF0 DTA
0 0
R/W R/W
15 to 0
28 27 26
— DREQS NRD
0 0
R/W R/W R/W
20 19 18
— ERRF —
0 0
R R/(W)*
12 11 10
TSEIE —
0 0
R/W R/W
4 3
— — DMAP2
0 0
R R R/W
Settable Size
(Byte)
1 to 65,536
2 to 131,072
4 to 262,144
25 24
— —
0 0 0
R R
17 16
ESIF DTIF
0 0 0
R R/(W)* R/(W)*
9 8
ESIE DTIE
0 0 0
R R/W R/W
2 1 0
DMAP1 DMAP0
0 0 0
R/W R/W