Table of Contents
Advertisement
M30245 Group
2.4.5 Operation of Serial I/O (transmission used for SIM interface)
In transmitting data in UARTi (i=0 to 3) mode (used for SIM interface), choose functions from those listed
in Table 2.4.6. Operations of the circled items are described below. Figure 2.4.13 shows the operation
timing, and Figures 2.4.14 and 2.4.15 show the set-up procedures.
www.DataSheet4U.com
Operation
Note
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Table 2.4.6. Choosed functions
Item
Transfer data
Direct format
O
format
Inverse format
(1) Setting the transmit enable bit and receive enable bit to "1" and writing transmission data to
the UARTi (i=0 to 3) transmit buffer register readies the data transmissible status. Set UARTi
(i=0 to 3) transfer interrupt for being enabled.
(2) Transmission data held in the UARTi (i=0 to 3) transmit buffer register is transmitted to the
UARTi (i=0 to 3) transmit register. At this time, the first bit (the start bit) of the transmission
data is transmitted from the TxDi (i=0 to 3) pin. Then, data is transmitted, bit by bit, in se-
quence: LSB, ····, MSB, parity bit, and stop bit(s).
(3) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to "1", which
indicates that transmission is completed. At this time, the UARTi (i=0 to 3) transmit interrupt
request bit goes to "1". The transfer clock stops at "H" level.
(4) If the transmission condition of the next data is ready when transmission is completed, a start
bit is generated following to stop bit(s), and the next data is transmitted.
(5) If a parity error occurs, an L is output from the SIM card, and the RxDi (i=0 to 3) terminal turns
to "L" level. Check the RxDi (i=0 to 3) terminal's level within the UARTi (i=0 to 3) transmission
interrupt routine, and if it is found to be at the "L" level, then handle the error.
• The parity error level is determined within a UARTi (i=0 to 3) transmission interrupt. When a
transmission interrupt request occurs, set the priority level of the transmission interrupt higher
than those of other interrupts so that the interrupt routine can be immediately carried out.
Either in the main routine or in an interrupt routine, the interrupt inhibition time has to be made
as short as possible.
• Set the RxDi (i=0 to 3) pin's port direction register to input.
• Select N-channel open drain output for TxDi pin with data output select bit of UARTi (i=0 to 3)
transmit/receive control register 0.
page 73 of 354
Set-up
Item
Transfer clock
source
2. SIM interface
Set-up
Internal clock (f
/f
/f
)
O
1
8
32
External clock (CLKi pin)
Advertisement
Table of Contents
