Pins Used For Dram Interface; Table 6.6 Dram Interface Pins - Renesas H8S/2368 Series Hardware Manual

6.6.4

Pins Used for DRAM Interface

Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2, CS5 pins
are in the input state after a reset, set the corresponding DDR to 1 when RAS2, RAS5 signals are
output.
Table 6.6 DRAM Interface Pins
With DRAM
Pin Setting
HWR WE
CS2 RAS2
CS3 RAS3
UCAS UCAS
LCAS LCAS
RD, OE OE
WAIT WAIT
A15 to A0 A15 to A0
D15 to D0 D15 to D0
Rev. 2.00, 05/03, page 154 of 820
Name
Write enable
Row address strobe 2/
row address strobe
Row address strobe 3
Upper column address
strobe
Lower column address
strobe
Output enable
Wait
Address pins
Data pins
I/O Function
Output Write enable for DRAM space
access
Output Row address strobe when area 2
is designated as DRAM space or
row address strobe when areas
2 to 5 are designated as
continuous DRAM space
Output Row address strobe when area 3
is designated as DRAM space
Output Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access
Output Lower column address strobe
signal for 16-bit DRAM space
access
Output Output enable signal for DRAM
space access
Input Wait request signal
Output Row address/column address
multiplexed output
I/O Data input/output pins