Renesas H8SX/1650 Hardware Manual page 655

Bφ
A23 to A0
CS7 to CS0
AS
BS
RD/WR
Read
RD
D15 to D0
LUB, LLB
RD/WR
Write
RD
D15 to D0
Figure 20.13 Byte Control SRAM: 2-State Read/Write Access
T
1
t
AD
t
CSD1
t
AS1
t
t
ASD
ASD
t
t
BSD BSD
t
RWD
t
AS1
t
RSD1
t
AC5
t
RDS1
t
AA2
t
AC5
t
UBD
t
t
AS1
UBW1
t
RWD
High
t
WDD
Section 20 Electrical Characteristics
T
2
t
AH1
t
RWD
t
RSD1
t
RDH1
t
UBD
t
AH1
t
RWD
t
WDH1
Rev.2.00 Jun. 28, 2007 Page 633 of 666
REJ09B0311-0200