Renesas H8SX/1650 Hardware Manual page 363

Bit Bit Name
2 TGFC
1 TGFB
Initial
value R/W Description
0 R/(W)* Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/(W)* Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Section 9 16-Bit Timer Pulse Unit (TPU)
When TCNT = TGRC while TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
When DTC is activated by a TGIC interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFC after reading TGFC = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When TCNT = TGRB while TGRB is functioning as
output compare register
When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
When DTC is activated by a TGIB interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFB after reading TGFB = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Rev.2.00 Jun. 28, 2007 Page 341 of 666
REJ09B0311-0200