Usage Notes; Module Stop State Setting; Permissible Signal Source Impedance - Renesas H8SX/1650 Hardware Manual

Section 14 A/D Converter
14.7

Usage Notes

14.7.1

Module Stop State Setting

Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing the module stop state. For details, see section 18, Power-Down States.
14.7.2

Permissible Signal Source Impedance

This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input
signal for which the signal source impedance is 10 kΩ or less. This specification is provided to
enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
provided externally for conversion in single mode, the input load will essentially comprise only
the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since
a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal
with a large differential coefficient (e.g., 5 mV/µs or greater) (see figure 14.8). When converting a
high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted.
Sensor input
Rev.2.00 Jun. 28, 2007 Page 540 of 666
REJ09B0311-0200
Sensor output
impedance
R ≤ 10 kΩ
Low-pass
filter
C = 0.1 µF
(recommended value)
Figure 14.8 Example of Analog Input Circuit
This LSI
Equivalent circuit of the A/D converter
10 kΩ
Cin =
15 pF
20 pF