Renesas H8SX/1650 Hardware Manual page 378

Section 9 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Buffer Operation
(a)
When TGR is an output compare register
Figure 9.15 shows an operation example in which PWM mode 1 has been designated for channel
0, and buffer operation has been designated for TGRA and TGRC. The settings used in this
example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at
compare match B.
As buffer operation has been set, when compare match A occurs, the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time compare match A occurs.
For details on PWM modes, see section 9.4.5, PWM Modes.
TCNT value
TGRB_0
TGRA_0
H'0000
H'0200
TGRC_0
Transfer
TGRA_0
TIOCA
(b) When TGR is an input capture register
Figure 9.16 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges
have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
Rev.2.00 Jun. 28, 2007 Page 356 of 666
REJ09B0311-0200
H'0200
H'0450
H'0200
Figure 9.15 Example of Buffer Operation (1)
H'0450
H'0520
H'0450
H'0520
Time