Table of Contents
Advertisement
6.7.5
Wait Control
The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw)
in the same way as the basic bus interface.
(1)
Program Wait Insertion
From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3-
state access space in area units, according to the settings in WTCRA and WTCRB.
(2)
Pin Wait Insertion
For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is
cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For
details on DDR and ICR, see section 8, I/O ports.
Figure 6.25 shows an example of wait cycle insertion timing.
Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 183 of 666
REJ09B0311-0200
Advertisement
Table of Contents
