Endian And Data Alignment - Renesas H8SX/1650 Hardware Manual

(8)
Area 7
Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O
register area is external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 7 by the MPXE7 bit in MPXCR and the BCSEL7 bit in
SRAMCR. Table 6.14 shows the external interface of area 7.
Table 6.14 Area 7 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
6.5.6

Endian and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space.
MPXE7 of MPXCR
0
0
1
1
Section 6 Bus Controller (BSC)
Register Setting
BCSEL7 of SRAMCR
0
1
0
1
Rev.2.00 Jun. 28, 2007 Page 163 of 666
REJ09B0311-0200