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13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• When SMIF in SCMR = 0
Bit
7
Bit Name
TDRE
Initial Value
1
R/W
R/(W)*
Note: * Only 0 can be written, to clear the flag.
• When SMIF in SCMR = 1
Bit
7
Bit Name
TDRE
1
Initial Value
R/W
R/(W)*
Note: * Only 0 can be written, to clear the flag.
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit
Bit Name
7
TDRE
6
5
RDRF
ORER
0
0
R/(W)*
R/(W)*
6
5
RDRF
ORER
0
0
R/(W)*
R/(W)*
Initial
Value
R/W
Description
1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Section 13 Serial Communication Interface (SCI)
4
3
FRE
PER
0
0
R/(W)*
R/(W)*
4
3
ERS
PER
0
0
R/(W)*
R/(W)*
When the TE bit in SCR is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When a TXI interrupt request is issued allowing
DTC to write data to TDR
Rev.2.00 Jun. 28, 2007 Page 463 of 666
2
1
TEND
MPB
1
0
R
R
2
1
TEND
MPB
1
0
R
R
REJ09B0311-0200
0
MPBT
0
R/W
0
MPBT
0
R/W
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