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Table 2.14 Effective Address Calculation for Transfer and Operation Instructions
No.
Addressing Mode and Instruction Format
1
Immediate
op
IMM
Register direct
2
op
rm
rn
Register indirect
3
op
r
4
Register indirect with 16-bit displacement
op
r
disp
Register indirect with 32-bit displacement
op
r
disp
5
Index register indirect with 16-bit displacement
op
r
disp
Index register indirect with 32-bit displacement
op
r
disp
Register indirect with post-increment or post-decrement
6
op
r
Register indirect with pre-increment or pre-decrement
op
r
8-bit absolute address
7
op
aa
16-bit absolute address
op
aa
32-bit absolute address
op
aa
Effective Address Calculation
31
General register contents
31
General register contents
31
15
disp
Sign extension
31
General register contents
disp
31
Zero extension
Contents of general register
(RL, R, or ER)
31
15
disp
Sign extension
31
Zero extension
Contents of general register
(RL, R, or ER)
31
disp
31
General register contents
31
General register contents
31
7
SBR
31
15
Sign extension
aa
31
aa
Effective Address (EA)
0
31
0
31
+
0
0
31
+
0
×
1, 2, or 4
31
+
0
0
1, 2, or 4
×
31
+
0
0
31
±
1, 2, or 4
0
31
±
1, 2, or 4
0
31
aa
0
31
0
31
Rev.2.00 Jun. 28, 2007 Page 57 of 666
Section 2 CPU
0
0
0
0
0
0
0
0
0
0
REJ09B0311-0200
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