Renesas H8SX/1650 Hardware Manual page 82

Section 2 CPU
Request for exception
handling
A transition to the reset state occurs whenever the RES signal goes low.
Note: *
A transition can also be made to the reset state when the watchdog timer
overflows.
Rev.2.00 Jun. 28, 2007 Page 60 of 666
REJ09B0311-0200
RES = high
Exception-handling
Interrupt
state
request
End of exception
handling
Program execution
state
Figure 2.16 State Transitions
Reset state*
RES = low
Bus-released state
Bus
request
Bus request
End of
bus request
Program stop state
SLEEP instruction
End of bus request