Renesas H8SX/1650 Hardware Manual page 17

10.3.2 Output Data Registers H, L (PODRH, PODRL)............................................... 394
10.3.3 Next Data Registers H, L (NDRH, NDRL) ...................................................... 395
10.3.4 PPG Output Control Register (PCR) ................................................................ 398
10.3.5 PPG Output Mode Register (PMR) .................................................................. 399
10.4 Operation .......................................................................................................................... 401
10.4.1 Output Timing................................................................................................... 401
10.4.2 Sample Setup Procedure for Normal Pulse Output........................................... 402
10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............ 403
10.4.4 Non-Overlapping Pulse Output......................................................................... 404
10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ........................... 406
10.4.6 Example of Non-Overlapping Pulse Output
(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .......... 407
10.4.7 Inverted Pulse Output ....................................................................................... 409
10.4.8 Pulse Output Triggered by Input Capture ......................................................... 410
10.5 Usage Notes ...................................................................................................................... 410
10.5.1 Module Stop State Setting ................................................................................ 410
10.5.2 Operation of Pulse Output Pins......................................................................... 410
Section 11 8-Bit Timers (TMR).........................................................................411
11.1 Features............................................................................................................................. 411
11.2 Input/Output Pins.............................................................................................................. 414
11.3 Register Descriptions........................................................................................................ 415
11.3.1 Timer Counter (TCNT)..................................................................................... 416
11.3.2 Time Constant Register A (TCORA)................................................................ 416
11.3.3 Time Constant Register B (TCORB) ................................................................ 417
11.3.4 Timer Control Register (TCR).......................................................................... 417
11.3.5 Timer Counter Control Register (TCCR) ......................................................... 419
11.3.6 Timer Control/Status Register (TCSR)............................................................. 421
11.4 Operation .......................................................................................................................... 425
11.4.1 Pulse Output...................................................................................................... 425
11.4.2 Reset Input ........................................................................................................ 426
11.5 Operation Timing.............................................................................................................. 427
11.5.1 TCNT Count Timing ........................................................................................ 427
11.5.2 Timing of CMFA and CMFB Setting at Compare Match................................. 427
11.5.3 Timing of Timer Output at Compare Match ..................................................... 428
11.5.4 Timing of Counter Clear by Compare Match ................................................... 428
11.5.5 Timing of TCNT External Reset....................................................................... 429
11.5.6 Timing of Overflow Flag (OVF) Setting .......................................................... 429
11.6 Operation with Cascaded Connection............................................................................... 430
11.6.1 16-Bit Counter Mode ........................................................................................ 430
Rev.2.00 Jun. 28, 2007 Page xvii of xxii