Address Cycle Control - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.9.6

Address Cycle Control

An extension cycle (Tmaw) can be inserted between Tma1 and Tma2 cycles to extend the AH
signal output period by setting the ADDEX bit in MPXCR. By inserting the Tmaw cycle, the
address setup for AH and the AH minimum pulse width can be assured.
Figure 6.30 shows the access timing when the address cycle is three cycles.
Bφ
Address bus
CSn
AH
RD
Read
D15 to D0
LHWR
LLWR
Write
D15 to D0
BS
RD/WR
Note: n = 3 to 7
Figure 6.30 Access Timing of 3 Address Cycles (ADDEX = 1)
Rev.2.00 Jun. 28, 2007 Page 194 of 666
REJ09B0311-0200
Address cycle
T
T
ma1 maw
Address
Address
Data cycle
T
T
ma2 1
Write data
T
2
Read data