Renesas H8SX/1650 Hardware Manual page 20

13.9 Usage Notes ...................................................................................................................... 519
13.9.1 Module Stop State Setting ................................................................................ 519
13.9.2 Break Detection and Processing ....................................................................... 519
13.9.3 Mark State and Break Detection ....................................................................... 519
13.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ................................................................. 519
13.9.5 Relation between Writing to TDR and TDRE Flag .......................................... 520
13.9.6 Restrictions on Using DTC............................................................................... 520
13.9.7 SCI Operations during Power-Down State ....................................................... 521
Section 14 A/D Converter ................................................................................. 525
14.1 Features............................................................................................................................. 525
14.2 Input/Output Pins.............................................................................................................. 527
14.3 Register Descriptions........................................................................................................ 527
14.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 528
14.3.2 A/D Control/Status Register (ADCSR) ............................................................ 529
14.3.3 A/D Control Register (ADCR) ......................................................................... 531
14.4 Operation .......................................................................................................................... 532
14.4.1 Single Mode...................................................................................................... 532
14.4.2 Scan Mode ........................................................................................................ 533
14.4.3 Input Sampling and A/D Conversion Time ...................................................... 535
14.4.4 External Trigger Input Timing.......................................................................... 537
14.5 Interrupt Source ................................................................................................................ 537
14.6 A/D Conversion Accuracy Definitions ............................................................................. 538
14.7 Usage Notes ...................................................................................................................... 540
14.7.1 Module Stop State Setting ................................................................................ 540
14.7.2 Permissible Signal Source Impedance .............................................................. 540
14.7.3 Influences on Absolute Accuracy ..................................................................... 541
14.7.4 Setting Range of Analog Power Supply and Other Pins................................... 541
14.7.5 Notes on Board Design ..................................................................................... 541
14.7.6 Notes on Noise Countermeasures ..................................................................... 542
14.7.7 A/D Input Hold Function in Software Standby Mode ...................................... 543
Section 15 D/A Converter ................................................................................. 545
15.1 Features............................................................................................................................. 545
15.2 Input/Output Pins.............................................................................................................. 546
15.3 Register Descriptions........................................................................................................ 546
15.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 546
15.3.2 D/A Control Register 01 (DACR01) ................................................................ 547
15.4 Operation .......................................................................................................................... 549
Rev.2.00 Jun. 28, 2007 Page xx of xxii