Renesas H8SX/1650 Hardware Manual page 362

Section 9 16-Bit Timer Pulse Unit (TPU)
Bit Bit Name
4 TCFV
3 TGFD
Rev.2.00 Jun. 28, 2007 Page 340 of 666
REJ09B0311-0200
Initial
value R/W Description
0 R/(W)* Overflow Flag
Status flag that indicates that a TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from H'FFFF
to H'0000)
[Clearing condition]
When a 0 is written to TCFV after reading TCFV = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
0 R/(W)* Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When TCNT = TGRD while TGRD is functioning as
output compare register
When TCNT value is transferred to TGRD by input
capture signal while TGRD is functioning as input
capture register
When DTC is activated by a TGID interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFD after reading TGFD = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)