Operation; Output Timing - Renesas H8SX/1650 Hardware Manual

10.4

Operation

Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to 16 bits is possible by writing new output data to NDR before the next
compare match.
Pulse output pin
10.4.1

Output Timing

If pulse output is enabled, the NDR contents are transferred to PODR and output when the
specified compare match event occurs. Figure 10.3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
Pφ
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)
Normal output/inverted output
Figure 10.2 Schematic Diagram of PPG
TCNT
TGRA
Compare match
A signal
NDRH
PODRH
PO8 to PO15
Section 10 Programmable Pulse Generator (PPG)
NDER
Q
Output trigger signal
C
Q PODR D Q NDR
N N + 1
N
n
m
m
Rev.2.00 Jun. 28, 2007 Page 401 of 666
Internal data bus
D
n
n
REJ09B0311-0200