Renesas H8SX/1650 Hardware Manual page 180

Section 6 Bus Controller (BSC)
(d) Address/data multiplexed I/O interface
The number of access cycles in data cycle of the address/data multiplexed I/O interface is the
same as that in the basic bus interface. The number of access cycles in address cycle can be
specified as two or three cycles by the ADDEX bit in MPXCR.
Number of access cycles in the address/data multiplexed I/O interface
= number of address output cycles (2, 3) + number of data output cycles (2, 3)
+ number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+number of external wait cycles by the WAIT pin]
Table 6.6 lists the number of access cycles for each interface.
Table 6.6 Number of Access Cycles
Basic bus interface
Byte control SRAM interface
Burst ROM interface
Address/data multiplexed I/O
interface
[Legend]
Numbers: Number of access cycles
Pin wait (0 to ∞)
n:
m: Number of burst accesses (0 to 63)
(e)
Strobe Assert/Negate Timings
The assert and negate timings of the strobe signals can be modified as well as number of access
cycles.
• Read strobe (RD) in the basic bus interface
• Chip select assertion period extension cycles in the basic bus interface
Rev.2.00 Jun. 28, 2007 Page 158 of 666
REJ09B0311-0200
= Th +T1 +T2
[0,1] [1] [1]
= Th +T1 +T2
[0,1] [1] [1]
= Th +T1 +T2
[0,1] [1] [1]
= Th +T1 +T2
[0,1] [1] [1]
= Th +T1 +T2
[0,1] [1] [1]
= Th +T1 +T2
[0,1] [1] [1]
= Tma +Th +T1 +T2
[2,3] [0,1] [1] [1]
= Tma +Th +T1 +T2
[2,3] [0,1] [1] [1]
+Tt
[0,1]
+Tpw +TtW +T3 +Tt
[0 to 7] [n] [1] [0,1]
+Tt
[0,1]
+Tpw +TtW +T3 +Tt
[0 to 7] [n] [1] [0,1]
+Tpw +TtW +T3
[0 to 7] [n] [1]
+Tt
[0,1]
+Tpw +TtW +T3 +Tt
[0 to 7] [n] [1] [0,1]
[3 to 12 + n]
[3 to 12 + n]
+Tb
[(1 to 8) × m] [(2 to 3) + (1 to 8) × m]
+Tb
[(1 to 8) × m] [(3 to 11 + n) + (1 to 8) × m]
[5 to 15 + n]
[2 to 4]
[2 to 4]
[4 to 7]