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Section 18 Power-Down States
• MSTPCRA
Bit
Bit Name
15
ACSE
14
MSTPA14
13
MSTPA13
12
MSTPA12 0
11
MSTPA11
10
MSTPA10
9
MSTPA9
8
MSTPA8
7
MSTPA7
6
MSTPA6
5
MSTPA5
4
MSTPA4
3
MSTPA3
2
MSTPA2
1
MSTPA1
0
MSTPA0
Rev.2.00 Jun. 28, 2007 Page 570 of 666
REJ09B0311-0200
Initial
Value
R/W
Module
0
R/W
All-Module-Clock-Stop Mode Enable
Enables/disables all-module-clock-stop mode to reduce
current consumption by stopping the bus controller and
I/O ports operations when the CPU executes the SLEEP
instruction after the module stop state has been set for all
the on-chip peripheral modules controlled by MSTPCR.
0: All-module-clock-stop mode disabled
1: All-module-clock-stop mode enabled
0
R/W
Reserved
0
R/W
These bits are always read as 0. The write value should
always be 0.
R/W
Data transfer controller (DTC)
1
R/W
Reserved
1
R/W
These bits are always read as 1. The write value should
always be 1.
1
R/W
8-bit timer (TMR_3 and TMR_2)
1
R/W
8-bit timer (TMR_1 and TMR_0)
1
R/W
Reserved
1
R/W
These bits are always read as 1. The write value should
always be 1.
1
R/W
D/A converter (channels 1 and 0)
1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
1
R/W
A/D converter (unit 0)
1
R/W
Reserved
1
R/W
These bits are always read as 1. The write value should
always be 1.
1
R/W
16-bit timer pulse unit (TPU channels 5 to 0)
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