Non-Overlapping Pulse Output - Renesas H8SX/1650 Hardware Manual

Section 10 Programmable Pulse Generator (PPG)
1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to
select compare match in the TPU channel set up in the previous step to be the output trigger.
Write output data H'80 in NDRH.
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by
writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts.
If the DTC is set for activation by the TGIA interrupt, pulse output can be obtained without
imposing a load on the CPU.
10.4.4

Non-Overlapping Pulse Output

During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• At compare match A, the NDR bits are always transferred to PODR.
• At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are
not transferred if their value is 1.
Figure 10.6 illustrates the non-overlapping pulse output operation.
Pulse
output
pin
Rev.2.00 Jun. 28, 2007 Page 404 of 666
REJ09B0311-0200
NDER
Q
C
Q PODR
Normal output/inverted output
Figure 10.6 Non-Overlapping Pulse Output
D Q NDR
Compare match A
Compare match B
Internal data bus
D