Renesas H8SX/1650 Hardware Manual page 170

Section 6 Bus Controller (BSC)
Iφ
Bφ
Address
CSn
AS
RD
Read D15 to D8
D7 to D0
LHWR
LLWR
Write
D15 to D8
D7 to D0
BS
RD/WR
Figure 6.5 System Clock: External Bus Clock = 4:1, External 2-State Access
Rev.2.00 Jun. 28, 2007 Page 148 of 666
REJ09B0311-0200
Divided clock
synchronization
cycle
T
sy
T T
1 2