Renesas H8SX/1650 Hardware Manual page 138

Section 5 Interrupt Controller
Table 5.7 shows the CPU priority control.
Table 5.7 CPU Priority Control
Interrupt
Control
Interrupt
Mode Priority
0 Default
2 IPR setting
Table 5.8 shows a setting example of the priority control function over the DTC and the transfer
request control state.
Table 5.8 Example of Priority Control Function Setting and Control State
Interrupt Control CPUPCE in
Mode CPUPCR
0 0
1
2 0
1
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Interrupt IPSETE in
Mask Bit CPUPCR
I = any 0
I = 0 1
I = 1
I2 to I0 0
1
CPUP2 to
CPUP0
Any
B'000
B'100
B'100
B'100
B'000
Any
B'000
B'000
B'011
B'100
B'101
B'110
B'111
B'101
B'101
Control Status
CPUP2 to CPUP0
B'111 to B'000
B'000
B'100
B'111 to B'000
I2 to I0
Transfer Request Control State
DTCP2 to
DTCP0 DTC
Any Enabled
B'000 Enabled
B'000 Masked
B'000 Masked
B'111 Enabled
B'111 Enabled
Any Enabled
B'000 Enabled
B'011 Enabled
B'011 Enabled
B'011 Masked
B'011 Masked
B'011 Masked
B'011 Masked
B'011 Masked
B'110 Enabled
Updating of CPUP2
to CPUP0
Enabled
Disabled
Enabled
Disabled