Usage Notes; Notes On Setting Cycle; Conflict Between Tcnt Write And Clear - Renesas H8SX/1650 Hardware Manual

Section 11 8-Bit Timers (TMR)
11.8

Usage Notes

11.8.1

Notes on Setting Cycle

If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in
which the values of TCNT and TCOR match. TCNT updates the counter value at this last state.
Therefore, the counter frequency is obtained by the following formula.
f = / (N + 1 )
f: Counter frequency
: Operating frequency
N: TCOR value
11.8.2

Conflict between TCNT Write and Clear

If a counter clear signal is generated during the T
priority and the write is not performed as shown in figure 11.13.
P
Address
Internal write signal
Counter clear signal
TCNT
Figure 11.13 Conflict between TCNT Write and Clear
Rev.2.00 Jun. 28, 2007 Page 432 of 666
REJ09B0311-0200
state of a TCNT write cycle, the clear takes
2
TCNT write cycle by CPU
T T
1 2
TCNT address
N H'00