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Section 9 16-Bit Timer Pulse Unit (TPU)
Input/output pins
Channel 3:
TIOCA3
TIOCB3
TIOCC3
TIOCD3
Channel 4:
TIOCA4
TIOCB4
Channel 5:
TIOCA5
TIOCB5
Clock input
Internal clock:
P /1
P /4
P /16
P /64
P /256
P /1024
P /4096
External clock:
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1:
TIOCA1
TIOCB1
Channel 2:
TIOCA2
TIOCB2
[Legend]
TSTR:
Timer start register
TSYR:
Timer synchronous register
TCR:
Timer control register
TMDR:
Timer mode register
TIOR (H, L):
Timer I/O control registers (H, L)
Rev.2.00 Jun. 28, 2007 Page 308 of 666
REJ09B0311-0200
TIER:
TSR:
TGR (A, B, C, D): Timer general registers (A, B, C, D)
TCNT:
Figure 9.1 Block Diagram of TPU
Interrupt request signals
Internal data bus
A/D conversion
start request signal
PPG output trigger signal
Interrupt request signals
Timer interrupt enable register
Timer status register
Timer counter
Channel 3:
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4:
TGI4A
TGI4B
TCI4V
TCI4U
Channel 5:
TGI5A
TGI5B
TCI5V
TCI5U
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1:
TGI1A
TGI1B
TCI1V
TCI1U
Channel 2:
TGI2A
TGI2B
TCI2V
TCI2U
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