Timer Synchronous Register (Tsyr) - Renesas H8SX/1650 Hardware Manual

9.3.9

Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit 7
Bit Name
Initial Value 0
R/W R/W
Bit Bit Name

7, 6
5 SYNC5
4 SYNC4
3 SYNC3
2 SYNC2
1 SYNC1
0 SYNC0
6 5
SYNC5
0 0
R/W R/W
Initial
value R/W Description
All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W Timer Synchronization 5 to 0
0 R/W These bits select whether operation is independent of or
synchronized with other channels.
0 R/W
When synchronous operation is selected, synchronous
0 R/W
presetting of multiple channels, and synchronous clearing
0 R/W
through counter clearing on another channel are possible.
0 R/W
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous
clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to
CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operate independently (TCNT
1: TCNT_5 to TCNT_0 perform synchronous operation
Section 9 16-Bit Timer Pulse Unit (TPU)
4 3
SYNC4 SYNC3
0 0
R/W R/W
presetting/clearing is unrelated to other channels)
(TCNT synchronous presetting/synchronous clearing
is possible)
Rev.2.00 Jun. 28, 2007 Page 345 of 666
2 1
SYNC2 SYNC1
0 0
R/W R/W
REJ09B0311-0200
0
SYNC0
0
R/W