Basic Timing - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.9.5

Basic Timing

The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR,
ASTCR, WTCRA, WTCRB, RDNCR, and CSACR.
Figures 6.28 and 6.29 show the basic access timings.
Read
Write
Figure 6.28 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1)
Rev.2.00 Jun. 28, 2007 Page 192 of 666
REJ09B0311-0200
Address cycle
T
ma1
Bφ
Address bus
CSn
AH
RD
D7 to D0
LLWR
D7 to D0
BS
RD/WR
Note: n = 3 to 7
Data cycle
T
T
ma2 1
Address
Address
T
2
Read data
Write data