Renesas R5S61650C Manuals

Manuals and User Guides for Renesas R5S61650C. We have 1 Renesas R5S61650C manual available for free PDF download: Hardware Manual

Renesas R5S61650C Hardware Manual (692 pages)

Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Brand: Renesas | Category: Computer Hardware | Size: 4.61 MB

How to Use this Manual
5
Table of Contents
9
Section 1 Overview

23
- Features
  23
  - Applications
    23
  - Overview of Functions
    24
- List of Products
  29
- Block Diagram
  30
- Pin Assignments
  31
- Pin Functions
  32
Section 2 CPU

37
Section 3 MCU Operating Modes

83
- Operating Mode Selection
  83
- Register Descriptions
  84
  - Mode Control Register (MDCR)
    84
  - System Control Register (SYSCR)
    86
- Operating Mode Descriptions
  88
  - Mode 4
    88
  - Mode 5
    88
  - Pin Functions
    89
- Address Map
  90
  - Address Map (Advanced Mode)
    90
Section 4 Exception Handling

91
- Exception Handling Types and Priority
  91
- Exception Sources and Exception Handling Vector Table
  92
- Reset
  94
- Traces Exception Handling
  97
- Address Error
  98
  - Address Error Source
    98
  - Address Error Exception Handling
    99
- Interrupts
  100
  - Interrupt Sources
    100
  - Interrupt Exception Handling
    100
- Instruction Exception Handling
  101
- Stack Status after Exception Handling
  104
- Usage Note
  105
Section 5 Interrupt Controller

107
Section 6 Bus Controller (BSC)

143
- Features
  143
- Register Descriptions
  146
- Bus Configuration
  167
- Multi-Clock Function and Number of Access Cycles
  168
- External Bus
  172
  - Input/Output Pins
    172
  - Area Division
    175
  - Chip Select Signals
    176
  - External Bus Interface
    177
  - Area and External Bus Interface
    181
  - Endian and Data Alignment
    185
- Basic Bus Interface
  189
  - Data Bus
    189
  - I/O Pins Used for Basic Bus Interface
    189
  - Basic Timing
    190
  - Wait Control
    196
  - Read Strobe (RD) Timing
    198
  - Extension of Chip Select (CS) Assertion Period
    199
- Byte Control SRAM Interface
  201
  - Byte Control SRAM Space Setting
    201
  - Data Bus
    201
  - I/O Pins Used for Byte Control SRAM Interface
    202
  - Basic Timing
    203
  - Wait Control
    205
  - Read Strobe (RD)
    207
  - Extension of Chip Select (CS) Assertion Period
    207
- Burst ROM Interface
  207
  - Burst ROM Space Setting
    207
  - Data Bus
    208
  - I/O Pins Used for Burst ROM Interface
    208
  - Basic Timing
    209
  - Wait Control
    211
  - Read Strobe (RD) Timing
    211
  - Extension of Chip Select (CS) Assertion Period
    211
- Address/Data Multiplexed I/O Interface
  211
  - Address/Data Multiplexed I/O Space Setting
    211
  - Address/Data Multiplex
    212
  - Data Bus
    212
  - I/O Pins Used for Address/Data Multiplexed I/O Interface
    213
  - Basic Timing
    214
  - Address Cycle Control
    216
  - Wait Control
    217
  - Read Strobe (RD) Timing
    217
  - Extension of Chip Select (CS) Assertion Period
    218
- Idle Cycle
  220
  - Operation
    220
  - Pin States in Idle Cycle
    228
- Bus Release
  229
  - Operation
    229
  - Pin States in External Bus Released State
    230
  - Transition Timing
    231
- Internal Bus
  232
  - Access to Internal Address Space
    232
- Write Data Buffer Function
  233
  - Write Data Buffer Function for External Data Bus
    233
  - Write Data Buffer Function for Peripheral Modules
    234
- Bus Arbitration
  235
  - Operation
    235
  - Bus Transfer Timing
    236
- Bus Controller Operation in Reset
  237
- Usage Notes
  237
Section 7 Data Transfer Controller (DTC)

239
- Features
  239
- Register Descriptions
  241
- Activation Sources
  249
- Location of Transfer Information and DTC Vector Table
  250
- Operation
  253
  - Bus Cycle Division
    255
  - Transfer Information Read Skip Function
    257
  - Transfer Information Writeback Skip Function
    258
  - Normal Transfer Mode
    258
  - Repeat Transfer Mode
    259
  - Block Transfer Mode
    261
  - Chain Transfer
    262
  - Operation Timing
    263
  - Number of DTC Execution Cycles
    265
  - DTC Bus Release Timing
    266
  - DTC Priority Level Control to the CPU
    266
- DTC Activation by Interrupt
  267
- Examples of Use of the DTC
  268
  - Normal Transfer Mode
    268
  - Chain Transfer
    269
  - Chain Transfer When Counter = 0
    270
- Interrupt Sources
  271
- Usage Notes
  271
  - Module Stop State Setting
    271
  - On-Chip RAM
    272
  - DTCE Bit Setting
    272
  - Chain Transfer
    272
  - Transfer Information Start Address, Source Address, and Destination Address
    272
  - Endian
    272
Section 8 I/O Ports

273
- Register Descriptions
  279
- Output Buffer Control
  284
  - Port 1
    284
  - Port 2
    287
  - Port 3
    291
  - Port 5
    295
  - Port 6
    296
  - Port a
    298
  - Port B
    302
  - Port D
    304
  - Port E
    304
  - Port F
    305
  - Port H
    308
  - Port I
    308
- Port Function Controller
  314
- Usage Notes
  325
  - Notes on Input Buffer Control Register (ICR) Setting
    325
  - Notes on Port Function Control Register (PFCR) Settings
    325
Section 9 16-Bit Timer Pulse Unit (TPU)

327
- Features
  327
- Input/Output Pins
  331
- Register Descriptions
  332
  - Timer Control Register (TCR)
    334
  - Timer Mode Register (TMDR)
    340
  - Timer I/O Control Register (TIOR)
    341
  - Timer Interrupt Enable Register (TIER)
    359
  - Timer Status Register (TSR)
    361
  - Timer Counter (TCNT)
    365
  - Timer General Register (TGR)
    365
  - Timer Start Register (TSTR)
    366
  - Timer Synchronous Register (TSYR)
    367
- Operation
  368
  - Basic Functions
    368
  - Synchronous Operation
    374
  - Buffer Operation
    376
  - Cascaded Operation
    379
  - PWM Modes
    381
  - Phase Counting Mode
    386
- Interrupt Sources
  392
- DTC Activation
  394
- A/D Converter Activation
  394
- Operation Timing
  395
  - Input/Output Timing
    395
  - Interrupt Signal Timing
    399
- Usage Notes
  403
Section 10 Programmable Pulse Generator (PPG)

411
Section 11 8-Bit Timers (TMR)

433
- Features
  433
- Input/Output Pins
  436
- Register Descriptions
  437
  - Timer Counter (TCNT)
    438
  - Time Constant Register a (TCORA)
    438
  - Time Constant Register B (TCORB)
    439
  - Timer Control Register (TCR)
    439
  - Timer Counter Control Register (TCCR)
    441
  - Timer Control/Status Register (TCSR)
    443
- Operation
  447
  - Pulse Output
    447
  - Reset Input
    448
- Operation Timing
  449
- Operation with Cascaded Connection
  452
  - 16-Bit Counter Mode
    452
  - Compare Match Count Mode
    452
- Interrupt Sources
  453
  - Interrupt Sources and DTC Activation
    453
  - A/D Converter Activation
    453
- Usage Notes
  454
Section 12 Watchdog Timer (WDT)

459
- Features
  459
- Input/Output Pin
  460
- Register Descriptions
  460
- Operation
  464
  - Watchdog Timer Mode
    464
  - Interval Timer Mode
    466
- Interrupt Source
  466
- Usage Notes
  467
Section 13 Serial Communication Interface (SCI)

471
- Features
  471
- Input/Output Pins
  473
- Register Descriptions
  474
  - Receive Shift Register (RSR)
    476
  - Receive Data Register (RDR)
    476
  - Transmit Data Register (TDR)
    476
  - Transmit Shift Register (TSR)
    477
  - Serial Mode Register (SMR)
    477
  - Serial Control Register (SCR)
    480
  - Serial Status Register (SSR)
    485
  - Smart Card Mode Register (SCMR)
    492
  - Bit Rate Register (BRR)
    493
  - Serial Extended Mode Register (SEMR)
    501
- Operation in Asynchronous Mode
  503
- Multiprocessor Communication Function
  514
  - Multiprocessor Serial Data Transmission
    516
  - Multiprocessor Serial Data Reception
    517
- Operation in Clocked Synchronous Mode
  520
- Operation in Smart Card Interface Mode
  528
- Interrupt Sources
  539
  - Interrupts in Normal Serial Communication Interface Mode
    539
  - Interrupts in Smart Card Interface Mode
    540
- Usage Notes
  541
Section 14 A/D Converter

547
- Features
  547
- Input/Output Pins
  549
- Register Descriptions
  549
- Operation
  554
  - Single Mode
    554
  - Scan Mode
    555
  - Input Sampling and A/D Conversion Time
    557
  - External Trigger Input Timing
    559
- Interrupt Source
  559
- A/D Conversion Accuracy Definitions
  560
- Usage Notes
  562
Section 15 D/A Converter

567
- Features
  567
- Input/Output Pins
  568
- Register Descriptions
  568
  - D/A Data Registers 0 and 1 (DADR0 and DADR1)
    568
  - D/A Control Register 01 (DACR01)
    569
- Operation
  571
- Usage Notes
  572
  - Module Stop State Setting
    572
  - D/A Output Hold Function in Software Standby Mode
    572
Section 16 RAM

573
Section 17 Clock Pulse Generator

575
- Register Description
  576
  - System Clock Control Register (SCKCR)
    576
- Oscillator
  579
  - Connecting Crystal Resonator
    579
  - External Clock Input
    580
- PLL Circuit
  580
- Frequency Divider
  580
- Usage Notes
  581
  - Notes on Clock Pulse Generator
    581
  - Notes on Resonator
    582
  - Notes on Board Design
    582
Section 18 Power-Down States

585
- Features
  585
- Register Descriptions
  587
- Multi-Clock Function
  595
- Module Stop Function
  595
- Sleep Mode
  596
  - Transition to Sleep Mode
    596
  - Clearing Sleep Mode
    596
- All-Module-Clock-Stop Mode
  597
- Software Standby Mode
  597
- Hardware Standby Mode
  602
  - Transition to Hardware Standby Mode
    602
  - Clearing Hardware Standby Mode
    602
  - Hardware Standby Mode Timing
    602
  - Timing Sequence at Power-On
    603
- Sleep Instruction Exception Handling
  604
- Bφ Clock Output Control
  607
- Usage Notes
  608
Section 19 List of Registers

609
- Register Addresses (Address Order)
  610
- Register Bits
  619
- Register States in each Operating Mode
  629
Section 20 Electrical Characteristics

639
- Absolute Maximum Ratings
  639
- DC Characteristics
  640
- AC Characteristics
  643
  - Clock Timing
    644
  - Control Signal Timing
    646
  - Bus Timing
    647
  - Timing of On-Chip Peripheral Modules
    662
- A/D Conversion Characteristics
  666
- D/A Conversion Characteristics
  667
Appendix

669
- Port States in each Pin State
  669
- Product Lineup
  672
- Package Dimensions
  673
- Treatment of Unused Pins
  674
Main Revisions and Additions in this Edition

677
Index

683

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Renesas R5S61650C Manuals

Renesas R5S61650C Hardware Manual (692 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 Data Transfer Controller (DTC)

Section 8 I/O Ports

Section 9 16-Bit Timer Pulse Unit (TPU)

Section 10 Programmable Pulse Generator (PPG)

Section 11 8-Bit Timers (TMR)

Section 12 Watchdog Timer (WDT)

Section 13 Serial Communication Interface (SCI)

Section 14 A/D Converter

Section 15 D/A Converter

Section 16 RAM

Section 17 Clock Pulse Generator

Section 18 Power-Down States

Section 19 List of Registers

Section 20 Electrical Characteristics

Appendix

Main Revisions and Additions in this Edition

Index

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