Cs Assertion Period Control Registers (Csacr) - Renesas H8SX/1650 Hardware Manual

Bφ
RD
RDNn = 0
Data
RD
RDNn = 1
Data
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)

CS Assertion Period Control Registers (CSACR)

6.2.5
CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address
signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O
interface are to be extended. Extending the assertion period of the CSn and address signals allows
the setup time and hold time of read strobe (RD) and write strobe (LHWR/LLWR) to be assured
and to make the write data setup time and hold time for the write strobe become flexible.
Bit 15
Bit Name CSXH7
Initial Value 0
R/W R/W
Bit 7
Bit Name CSXT7
Initial Value 0
R/W R/W
T
1
14 13
CSXH6 CSXH5
0 0
R/W R/W
6 5
CSXT6 CSXT5
0 0
R/W R/W
Bus cycle
T
2
12 11
CSXH4 CSXH3
0 0
R/W R/W
4 3
CSXT4 CSXT3
0 0
R/W R/W
Rev.2.00 Jun. 28, 2007 Page 133 of 666
Section 6 Bus Controller (BSC)
T
3
(n = 7 to 0)
10 9
CSXH2 CSXH1
0 0
R/W R/W
2 1
CSXT2 CSXT1
0 0
R/W R/W
REJ09B0311-0200
8
CSXH0
0
R/W
0
CSXT0
0
R/W