Renesas H8SX/1650 Hardware Manual page 171

Divided clock
synchronization
cycle
Iφ
Bφ
Address
CSn
AS
RD
Read
D15 to D8
D7 to D0
LHWR
LLWR
Write
D15 to D8
D7 to D0
BS
RD/WR
Figure 6.6 System Clock: External Bus Clock = 2:1, External 3-State Access
T T
sy 1
Section 6 Bus Controller (BSC)
T T
2 3
Rev.2.00 Jun. 28, 2007 Page 149 of 666
REJ09B0311-0200