Transfer Information Writeback Skip Function; Normal Transfer Mode - Renesas H8SX/1650 Hardware Manual

Section 7 Data Transfer Controller (DTC)
7.5.3

Transfer Information Writeback Skip Function

By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer
information will not be written back. This function is performed regardless of short or full address
mode. Table 7.5 shows the transfer information writeback skip condition and writeback skipped
registers. Note that the CRA and CRB are always written back regardless of the short or full
address mode. In addition in full address mode, the writeback of the MRA and MRB are always
skipped.
Table 7.5 Transfer Information Writeback Skip Condition and Writeback Skipped
Registers
SM1
0
0
1
1
7.5.4

Normal Transfer Mode

In normal transfer mode, one operation transfers one byte, one word, or one longword of data.
From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be
specified as incremented, decremented, or fixed. When the specified number of transfers ends, an
interrupt can be requested to the CPU.
Table 7.6 lists the register function in normal transfer mode. Figure 7.7 shows the memory map in
normal transfer mode.
Table 7.6 Register Function in Normal Transfer Mode
Register
SAR
DAR
CRA
CRB
Note: * Transfer information writeback is skipped.
Rev.2.00 Jun. 28, 2007 Page 236 of 666
REJ09B0311-0200
DM1
0
1
0
1
Function
Source address
Destination address
Transfer count A
Transfer count B
SAR
Skipped
Skipped
Written back
Written back
Written Back Value
Incremented/decremented/fixed*
Incremented/decremented/fixed*
CRA − 1
Not updated
DAR
Skipped
Written back
Skipped
Written back