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Table 7.3
Chain Transfer Conditions
1st Transfer
CHNE CHNS DISEL
0
0
0
0
0
1
1
0
1
1
0
1
1
1
1
1
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
mode
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode
7.5.1
Bus Cycle Division
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus
cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the
transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle
is divided and the transfer data is read from or written to in words.
Table 7.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and
access data size. Figure 7.5 shows the bus cycle division example.
Table 7.4
Number of Bus Cycle Divisions and Access Size
SAR and DAR Values Byte (B)
Address 4n
Address 2n + 1
Address 4n + 2
Transfer
1
Counter*
CHNE CHNS DISEL
Not 0
2
0*
0
0
0
Not 0
2
0*
0
0
0
Not 0
1 (B)
1 (B)
1 (B)
Section 7 Data Transfer Controller (DTC)
2nd Transfer
Transfer
Counter*
0
Not 0
2
0
0*
1
0
Not 0
2
0
0*
1
Specified Data Size
Word (W)
1 (W)
2 (B-B)
1 (W)
Rev.2.00 Jun. 28, 2007 Page 233 of 666
1
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU
Longword (LW)
1 (LW)
3 (B-W-B)
2 (W-W)
REJ09B0311-0200
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