Renesas H8SX/1650 Hardware Manual page 256

Section 7 Data Transfer Controller (DTC)
[Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word]
Clock
DTC activation
request
DTC request
Address
[Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]
Clock
DTC activation
request
DTC request
Address
[Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]
Clock
DTC activation
request
DTC request
Address
Rev.2.00 Jun. 28, 2007 Page 234 of 666
REJ09B0311-0200
B
Vector read Transfer information Data transfer Transfer information
read
B
Vector read Transfer information
read
W
Vector read Transfer information Data transfer Transfer information
read
Figure 7.5 Bus Cycle Division Example
R W
B W
write
R W
W B L
Data transfer Transfer information
write
R W
W L
write