Table of Contents
Advertisement
11.5
Operation Timing
11.5.1
TCNT Count Timing
Figure 11.5 shows the TCNT count timing for internal clock input. Figure 11.6 shows the TCNT
count timing for external clock input. Note that the external clock pulse width must be at least 1.5
states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
The counter will not increment correctly if the pulse width is less than these values.
P
Internal clock
TCNT input
clock
TCNT
Figure 11.5 Count Timing for Internal Clock Input at Falling Edge
P
External clock
input pin
TCNT input
clock
TCNT
Figure 11.6 Count Timing for External Clock Input at Falling and Rising Edges
11.5.2
Timing of CMFA and CMFB Setting at Compare Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT
values match, the compare match signal is not generated until the next TCNT clock input. Figure
11.7 shows this timing.
N – 1
N – 1
N
N
Rev.2.00 Jun. 28, 2007 Page 427 of 666
Section 11 8-Bit Timers (TMR)
N + 1
N + 1
REJ09B0311-0200
Advertisement
Table of Contents
