Renesas H8SX/1650 Hardware Manual page 465

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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TCNT value
H'FF
H'00
WT/IT = 1
TME = 1
WDTOVF signal
1
Internal reset signal *
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Figure 12.2 Operation in Watchdog Timer Mode
Overflow
WOVF = 1
H'00 written
to TCNT
WDTOVF and
internal reset are
generated
133 states *
519 states
Section 12 Watchdog Timer (WDT)
WT/IT = 1
H'00 written
TME = 1
to TCNT
2
Rev.2.00 Jun. 28, 2007 Page 443 of 666
REJ09B0311-0200
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