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Section 7 Data Transfer Controller (DTC)
Table 7.10 Number of Cycles Required for Each Execution State
Object to be Accessed
Bus width
Access cycles
Vector read S
Execu-
I
tion
Transfer information read S
status
Transfer information write S
Byte data read S
Word data read S
Longword data read S
Byte data write S
Word data write S
Longword data write S
Internal operation S
[Legend]
m:
Number of wait cycles 0 to 7 (For details, see section 6, Bus Controller (BSC).)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution cycles = I
7.5.10
DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, transfer information read, a single data transfer, or
transfer information writeback. The DTC does not release the bus during transfer information
read, single data transfer, or transfer information writeback.
7.5.11
DTC Priority Level Control to the CPU
The priority of the DTC activation sources over the CPU can be controlled by the CPU priority
level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits
DTCP2 to DTCP0. For details, see section 5, Interrupt Controller.
Rev.2.00 Jun. 28, 2007 Page 244 of 666
REJ09B0311-0200
On-
On-
Chip
Chip
RAM
ROM
32
32
1
1
1
1
1
1
J
1
1
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1
1
L
1
1
L
1
1
L
1
1
M
1
1
M
1
1
M
N
•
S
On-Chip I/O
Registers
8
16
32
2
2
2
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
+ Σ (J
•
•
S
+ K
S
+ L
I
J
K
External Devices
8
2
3
2
8
12 + 4m
4
8
12 + 4m
4
8
12 + 4m
4
2
3 + m
2
4
4 + 2m
2
8
12 + 4m
4
2
3 + m
2
4
4 + 2m
2
8
12 + 4m
4
1
•
•
S
+ M
S
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L
M
16
3
6 + 2m
6 + 2m
6 + 2m
3 + m
3 + m
6 + 2m
3 + m
3 + m
6 + 2m
•
S
N
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