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Section 9 16-Bit Timer Pulse Unit (TPU)
P
Address
Status flag
Period in which the next transfer request is masked
Interrupt request
signal
Figure 9.43 Timing for Status Flag Clearing by DTC Activation (1)
P
Address
Period in which the next transfer request is masked
Status flag
Interrupt
request signal
Figure 9.44 Timing for Status Flag Clearing by DTC Activation (2)
Rev.2.00 Jun. 28, 2007 Page 380 of 666
REJ09B0311-0200
DTC
DTC
read cycle
write cycle
T
T
T
T
1
2
1
Source
Destination
address
address
DTC
read cycle
Source address
Period of flag clearing
Period of interrupt request signal clearing
2
DTC
write cycle
Destination address
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