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Table 6.22 Idle Cycles in Mixed Accesses to Normal Space
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Next
Access
Access
Normal space
Normal
read
space read
Normal space
Normal
read
space write
Normal space
Normal
write
space read
IDLS
IDLSEL
2
1
0
7 to 0
0
1
0
1
0
1
0
1
0
1
Section 6 Bus Controller (BSC)
IDLCA
IDLCB
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Rev.2.00 Jun. 28, 2007 Page 205 of 666
Idle Cycle
Disabled
1 cycle inserted
2 cycles inserted
3 cycles inserted
4 cycles inserted
0 cycle inserted
2 cycle inserted
3 cycles inserted
4 cycles inserted
Disabled
1 cycle inserted
2 cycles inserted
3 cycles inserted
4 cycles inserted
0 cycle inserted
2 cycle inserted
3 cycles inserted
4 cycles inserted
Disabled
1 cycle inserted
2 cycles inserted
3 cycles inserted
4 cycles inserted
REJ09B0311-0200
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