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Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
5
TE
4
RE
3
MPIE
2
TEIE
1
CKE1
0
CKE0
Rev.2.00 Jun. 28, 2007 Page 462 of 666
REJ09B0311-0200
Initial
Value
R/W
Description
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled. Under
this condition, serial transmission is started by writing
transmit data to TDR, and clearing the TDRE flag in
SSR to 0. Note that SMR should be set prior to setting
the TE bit to 1 in order to designate the transmission
format.
If transmission is halted by clearing this bit to 0, the
TDRE flag in SSR is fixed 1.
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled. Under
this condition, serial reception is started by detecting
the start bit in asynchronous mode or the synchronous
clock input in clocked synchronous mode. Note that
SMR should be set prior to setting the RE bit to 1 in
order to designate the reception format.
Even if reception is halted by clearing this bit to 0, the
RDRF, FER, PER, and ORER flags are not affected
and the previous value is retained.
0
R/W
Multiprocessor Interrupt Enable (valid only when the MP
bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
0
R/W
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
0
R/W
Clock Enable 1, 0
0
R/W
These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 13.7.8, Clock Output Control.
•
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1X: Reserved
•
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
When GM in SMR = 0
When GM in SMR = 1
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