Section 4 Exception Handling; Exception Handling Types And Priority - Renesas H8SX/1650 Hardware Manual

4.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an
interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal
instruction or slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If
two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, see section 5, Interrupt Controller.
Table 4.1 Exception Types and Priority
Priority Exception Type
High Reset
Illegal instruction
1
Trace*
Address error
Interrupt
Sleep instruction
Trap instruction*
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests and sleep instruction exception handling
requests are accepted at all times in program execution state.

Section 4 Exception Handling

Exception Handling Start Timing
Exception handling starts at the timing of level change from
low to high on the RES pin, or when the watchdog timer
overflows. The CPU enters the reset state when the RES
pin is low.
Exception handling starts when an undefined code is
executed.
Exception handling starts after execution of the current
instruction or exception handling, if the trace (T) bit in EXR
is set to 1.
After an address error has occurred, exception handling
starts on completion of instruction execution.
Exception handling starts after execution of the current
instruction or exception handling, if an interrupt request has
occurred.*
Exception handling starts by execution of a sleep instruction
(SLEEP), if the SSBY bit in SBYCR is set to 0 and the
SLPIE bit in SBYCR is set to 1.
3
Exception handling starts by execution of a trap instruction
(TRAPA).
2
Rev.2.00 Jun. 28, 2007 Page 69 of 666
Section 4 Exception Handling
REJ09B0311-0200