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Section 7 Data Transfer Controller (DTC)
7.2
Register Descriptions
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the
CPU. The contents of these registers are stored in the data area as transfer information. When a
DTC activation request occurs, the DTC reads a start address of transfer information that is stored
in the data area according to the vector address, reads the transfer information, and transfers data.
After the data transfer, it writes a set of updated transfer information back to the data area.
• DTC enable registers A to H (DTCERA to DTCERH)
• DTC control register (DTCCR)
• DTC vector base register (DTCVBR)
Rev.2.00 Jun. 28, 2007 Page 219 of 666
REJ09B0311-0200
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