Renesas H8SX/1650 Hardware Manual page 11

4.5.2 Address Error Exception Handling ..................................................................... 77
4.6 Interrupts............................................................................................................................. 78
4.6.1 Interrupt Sources................................................................................................. 78
4.6.2 Interrupt Exception Handling ............................................................................. 78
4.7 Instruction Exception Handling .......................................................................................... 79
4.7.1 Trap Instruction Exception Handling.................................................................. 79
4.7.2 Sleep Instruction Exception Handling ................................................................ 80
4.7.3 Exception Handling by Illegal Instruction .......................................................... 81
4.8 Stack Status after Exception Handling................................................................................ 82
4.9 Usage Note.......................................................................................................................... 83
Section 5 Interrupt Controller ..............................................................................85
5.1 Features............................................................................................................................... 85
5.2 Input/Output Pins................................................................................................................ 87
5.3 Register Descriptions.......................................................................................................... 87
5.3.1 Interrupt Control Register (INTCR) ................................................................... 88
5.3.2 CPU Priority Control Register (CPUPCR) ......................................................... 89
5.3.3 Interrupt Priority Registers A to C, E to H, K, and L
(IPRA to IPRC, IPRE to IPRH, IPRK, and IPRL).............................................. 90
5.3.4 IRQ Enable Register (IER) ................................................................................. 92
5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................... 94
5.3.6 IRQ Status Register (ISR)................................................................................... 98
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................. 99
5.4 Interrupt Sources............................................................................................................... 100
5.4.1 External Interrupts ............................................................................................ 100
5.4.2 Internal Interrupts ............................................................................................. 101
5.5 Interrupt Exception Handling Vector Table...................................................................... 102
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 106
5.6.1 Interrupt Control Mode 0 .................................................................................. 106
5.6.2 Interrupt Control Mode 2 .................................................................................. 108
5.6.3 Interrupt Exception Handling Sequence ........................................................... 110
5.6.4 Interrupt Response Times ................................................................................. 111
5.6.5 DTC Activation by Interrupt............................................................................. 112
5.7 CPU Priority Control Function Over DTC ....................................................................... 115
5.8 Usage Notes ...................................................................................................................... 117
5.8.1 Conflict between Interrupt Generation and Disabling ...................................... 117
5.8.2 Instructions that Disable Interrupts ................................................................... 118
5.8.3 Times when Interrupts are Disabled ................................................................. 118
5.8.4 Interrupts during Execution of EEPMOV Instruction....................................... 118
5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions................ 118
Rev.2.00 Jun. 28, 2007 Page xi of xxii