Block Transfer Mode - Renesas H8SX/1650 Hardware Manual

7.5.6

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area by the DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one
block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR
when DTS = 0) specified as the block area is restored to the initial state. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When
the specified number of transfers ends, an interrupt is requested to the CPU.
Table 7.8 lists the register function in block transfer mode. Figure 7.9 shows the memory map in
block transfer mode.
Table 7.8 Register Function in Block Transfer Mode
Register Function
SAR Source address
DAR Destination address
CRAH Block size storage
CRAL Block size counter
CRB Block transfer counter
Note: * Transfer information writeback is skipped.
SAR
(When Transfer Destination is Specified as Block Area)
Written Back Value
DTS =0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DTS = 0: DAR initial value
DTS =1: Incremented/decremented/fixed*
CRAH
CRAH
CRB − 1
Transfer source data area
1st block
:
:
:
Nth block
Figure 7.9 Memory Map in Block Transfer Mode
Section 7 Data Transfer Controller (DTC)
Transfer destination data area
(specified as block area)
Transfer
Block area
Rev.2.00 Jun. 28, 2007 Page 239 of 666
DAR
REJ09B0311-0200