Renesas H8SX/1650 Hardware Manual page 577

Bit Bit Name
10 ICK2
9 ICK1
8 ICK0

7
6 PCK2
5 PCK1
4 PCK0

3
Initial
Value R/W Description
0 R/W System Clock (Iφ) Select
1 R/W These bits select the frequency of the system clock
provided to the CPU and DTC. The ratio to the input clock
0 R/W
is as follows:
000: × 4
001: × 2
010: × 1
011: × 1/2
1XX: Setting prohibited
The frequencies of the peripheral module clock and
external bus clock change to the same frequency as the
system clock if the frequency of the system clock is lower
than that of the two clocks.
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
0 R/W Peripheral Module Clock (Pφ) Select
1 R/W These bits select the frequency of the peripheral module
clock. The ratio to the input clock is as follows:
0 R/W
000: × 4
001: × 2
010: × 1
011: × 1/2
1XX: Setting prohibited
The frequency of the peripheral module clock should be
lower than that of the system clock. Though these bits
can be set so as to make the frequency of the peripheral
module clock higher than that of the system clock, the
clocks will have the same frequency in reality.
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
Section 17 Clock Pulse Generator
Rev.2.00 Jun. 28, 2007 Page 555 of 666
REJ09B0311-0200