Table of Contents
Advertisement
Section 18 Power-Down States
18.8
Hardware Standby Mode
18.8.1
Transition to Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this
LSI is in hardware standby mode.
18.8.2
Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is entered and clock oscillation is
started. Ensure that the RES pin is held low until clock oscillation settles (for details on the
oscillation settling time, refer to table 18.2). When the RES pin is subsequently driven high, a
transition is made to the program execution state via the reset exception handling state.
18.8.3
Hardware Standby Mode Timing
Figure 18.3 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,
waiting for the oscillation settling time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Rev.2.00 Jun. 28, 2007 Page 580 of 666
REJ09B0311-0200
Figure 18.3 Hardware Standby Mode Timing
Oscillation
Reset
settling time
exception handling
Advertisement
Table of Contents
