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(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is
activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by
the CPU, and figures 9.43 and 9.44 show the timing for status flag clearing by the DTC.
P
Address
Write
Status flag
Interrupt request
signal
The status flag and interrupt request signal are cleared in synchronization with Pφ after the DTC
transfer has started, as shown in figure 9.43. If conflict occurs for clearing the status flag and
interrupt request signal due to activation of multiple DTC transfers, it will take up to five clock
cycles (Pφ) for clearing them, as shown in figure 9.44. The next transfer request is masked for a
longer period of either a period until the current transfer ends or a period for five clock cycles (Pφ)
from the beginning of the transfer. Note that in the DTC transfer, the status flag may be cleared
during outputting the destination address.
Figure 9.42 Timing for Status Flag Clearing by CPU
Section 9 16-Bit Timer Pulse Unit (TPU)
TSR write cycle
T
T
1
2
TSR address
Rev.2.00 Jun. 28, 2007 Page 379 of 666
REJ09B0311-0200
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